Method of improving surface planarity of chemical-mechanical polishing operation by forming shallow dummy

ABSTRACT

A chemical-mechanical polishing method utilizes a shallow dummy pattern for planarizing a dielectric layer. The method includes the steps of first forming a shallow dummy pattern on the dielectric layer, and then coating a patterned photoresist layer over the dielectric layer. Thereafter, the photoresist layer is used as a mask to form openings in other areas of the dielectric layer. Subsequently, the photoresist layer is removed to expose the shallow dummy pattern, and then a glue/barrier layer and a conductive layer are sequentially deposited. Next, a chemical-mechanical polishing operation is carried out to remove excess conductive layer and glue/barrier layer above the dielectric layer as well as the shallow dummy pattern at the same time. Since the removal rate of glue/barrier layer in each area above the dielectric layer is about the same, a planar substrate surface is obtained.

BACKGROUND OF THE INVENTION

[0001] 1. Field of Invention

[0002] The present invention relates to a chemical-mechanical polishing(CMP) method, and more particularly, to a CMP method that is capable offorming a highly planar surface by forming a dummy pattern.

[0003] 2. Description of Related Art

[0004] As the level of integration of semiconductor devices increases,not enough area can be found on the surface of a silicon chip forforming all the necessary interconnects. To accommodate allinterconnects resulting from a miniaturization ofmetal-oxide-semiconductor (MOS) transistors, designs having two or moremetallic layers are frequently employed. An inter-metal dielectric (IMD)layer is normally used as an isolating layer separating an upper and alower metallic layer. The conductive line patterns of a metallic layerare normally buried within trenches, and connection between an upper anda lower conductive line pattern is achieved through a plug formed insidea via opening.

[0005] A conventional method of manufacturing interconnects includes thesteps of forming a via opening in an inter-metal dielectric (IMD) layer,and then completely filling the via opening with a conductive materialto form a plug. Thereafter, metallic lines are formed above the IMDlayer. The metallic lines are formed by depositing a layer of metal overthe IMD layer, and then performing conventional photolithographic andetching operations. However, when the metallic layer is etched,micro-bridges are frequently formed between neighboring metallic linesso that two metallic lines are linked, which leads to a short-circuitingcondition.

[0006] To improve the situation of the micro-bridging effect, themetallic lines are formed by a damascene process. The method is todeposit a dielectric layer over the IMD layer after the plug is formed.The dielectric layer has a thickness roughly equal to the thickness ofthe subsequently formed metallic lines. Next, the dielectric layer isetched to form a trench pattern, and then metallic material is depositedinto the trenches to form the metallic lines. Since there is no directetching of the metallic layer, there is no micro-bridging effect.

[0007] Another method for eliminating the micro-bridging effect is knownas a dual damascene process. Dual damascene process is very similar to adamascene process. The main difference is that a damascene process iscarried out after the plug is formed. On the other hand, the via openingand the trench pattern in a dual damascene process are formed at thesame time so that conductive material can be deposited in a singleoperation to form the interconnects.

[0008] For clarity of explanation, the trench pattern in a damasceneprocess and the via opening plus the trench pattern in a dual damasceneprocess will be referred to as “damascene pattern” from now on.

[0009] In both damascene and dual damascene process, the conductivematerial above the dielectric layer needs to be removed after thedamascene pattern is completely filled. A chemical-mechanical polishingmethod can be used to remove the excess conductive material above thedielectric layer while obtaining a planar surface at the same time.

[0010]FIGS. 1A through 1E are cross-sectional views showing theprogression of manufacturing steps in producing an interconnect thatuses a chemical-mechanical polishing method to remove excess metalaccording to a conventional dual damascene process.

[0011] First, as shown in FIG. 1A, a conductive layer 12 is formed overa substrate 10. Thereafter, a dielectric layer 14 and an etching stoplayer 16 are sequentially formed over the conductive layer 12. Thedielectric layer 14 can be a silicon oxide (SiO_(x)) layer, and theetching stop layer 16 can be a silicon nitride (SiN_(x)) layer, forexample. Then, a patterned photoresist layer 18 is formed over theetching stop layer 16. The patterned photoresist layer 18 is used formarking out the area for forming a via opening. Subsequently, theetching stop layer 16 is etched to form an opening using the photoresistlayer 18 as a mask. The etching stop layer 16 is later used as a maskfor patterning out the via opening.

[0012] Next, as shown in FIG. 1B, the photoresist layer 18 is removed,and then another dielectric layer 24 is formed over the etching stoplayer 16.

[0013] Next, as shown in FIG. 1C, another patterned photoresist layer 28is formed over the dielectric layer 24. The photoresist layer 28 is usedto pattern out the trench region in the dielectric layer 24. In thesubsequent step, a dry etching method, for example, is used to patternthe dielectric layer 24, thereby exposing the etching stop layer 16.Consequently, the dielectric layer 24 becomes a dielectric layer 24 ahaving an opening pattern or trench 25 within. Thereafter, using theetching stop layer 16 as a mask, the dry etching operation is continueduntil a portion of the conductive layer 12 is exposed. Hence, thedielectric layer 14 becomes a dielectric layer 14 a having a via opening23 within.

[0014] Next, as shown in FIG. 1D, the photoresist layer 28 is removed,and then a glue/barrier layer 21 conformal to the surface profile of thesubstrate 10 is formed over the substrate 10. The glue/barrier layer 21can be a tantalum nitride layer (TaN_(x)), for example. Subsequently, ametallic layer 22 is formed over the glue/barrier layer 21 completelyfilling the via opening 23 and the trench 25.

[0015] Next, as shown in FIG. 1E, a chemical-mechanical polishingoperation is carried out to remove excess metallic material andglue/barrier layer 21 above the dielectric layer 24 a. Hence, themetallic layer 22 becomes a metallic layer 22 a and the glue/barrierlayer 21 becomes a glue/barrier layer 21 a.

[0016] However, there is a direct relationship between over-polishingtime and polishing selectivity between the metallic layer 22 and theglue/barrier layer 21. When the polishing selectivity between the twolayers is large, polishing time needs to be extended. In general, themetallic layer 22 has a higher polishing rate than the glue/barrierlayer 21. Hence, when the glue/barrier layer 21 is exposed, the highermetallic content 22 a of damascene pattern in the dense area 27 makes iteasier to remove. Consequently, its neighboring glue/barrier layer 21 isalso easier to remove. On the other hand, the damascene pattern in theopen area 29 has a lower metallic content 22 a, thereby making itdifficult to remove.

[0017] In other words, the damascene pattern in the dense area 27 has ahigher rate of removal than the damascene pattern in the open area 29.Consequently, time necessary for completely removing the glue/barrierlayer 21 in the open area 29 will be greater than the time for removingthe same glue/barrier layer 21 in the dense area 27. In order to removecompletely the glue/barrier layer in the open area 29, areas such as thedense area 27 need to be over-polished. Therefore, an extra portion ofthe dielectric layer 24 a in the dense area 27 will be polished awayresulting in an eroded profile as shown in FIG. 1E.

[0018] One method of avoiding the erosion of dielectric layer 24 a inthe dense area 27 of a damascene pattern is to form a plurality of dummypatterns in the open area 29 of the damascene pattern. Consequently, thecombined dummy pattern and open area 29 density is roughly equivalent tothe density in the dense area 27. Hence, the rate of removal ofglue/barrier layer is roughly the same in both the dense area 27 and theopen area 29.

[0019]FIGS. 2A through 2C are cross-sectional views showing the steps inproducing an interconnect using a chemical-mechanical polishingoperation that has a higher polishing removal rate for a glue/barrierlayer in the open area of a damascene pattern.

[0020] Since the steps leading to the structure as shown in FIG. 2A hasalready been described in FIGS. 1A and 1B, detailed description ofprevious manufacturing steps are omitted. First, as shown in FIG. 2A, apatterned photoresist layer 38 is formed over the dielectric layer 24.The patterned photoresist layer 38 exposes the trench areas and dummypattern area of the dielectric layer 24. Next, a dry etching operationis carried out to etch the dielectric layer 24 using the photoresistlayer 38 as a mask. Consequently, the etching stop layer 16 is exposed,and the dielectric layer 24 is turned into a dielectric layer 24 bhaving openings that include trenches 25 and a dummy pattern 35.

[0021] Thereafter, using the exposed etching stop layer 16 as a mask,the dry etching operation is continued so that the dielectric layer 14becomes a dielectric layer 14 a having an opening or a via 23 within.Due to the presence of a dummy pattern 35 in the open area 29, thedensity of openings in the open area 29 is now similar to the density ofopenings in the dense area 27 of the dielectric layer 24 b.

[0022] Next, as shown in FIG. 2B, the photoresist layer 38 is removed,and then a glue/barrier layer 31 conformal to the surface profile of thesubstrate 10 is formed over the substrate 10. The glue/barrier layer 31can be a tantalum nitride layer (TaN_(x)), for example. Subsequently, ametallic layer 32 is formed over the glue/barrier layer 31 completelyfilling the via opening 23, the trenches 25, and the dummy pattern 35.

[0023] Next, as shown in FIG. 2C, a chemical-mechanical polishingoperation is carried out to remove excess metallic material andglue/barrier layer 31 above the dielectric layer 24 b. Hence, the filledvia opening 23 (FIG. 2B) becomes a plug 32 c, the filled trenches 25(FIG. 2B) become conductive lines 32 a, the filled dummy pattern 35(FIG. 2B) forms dummy conductive lines 32 b, and the glue/barrier layer31 becomes glue/barrier layers 31 a. In the presence of the dummyconductive lines 32 b, density of conductive lines 32 a in the densearea 27 is roughly the same as in the density of dummy conductive lines32 b in the open area 29. Consequently, polishing time can be shortened,and the problem of dielectric erosion in the dense area can be avoided.However, the dummy conductive lines 32 b increase the intra-metalparasitic capacitance, thereby affecting the transmission speed ofconductive lines.

[0024] In light of the foregoing, it is necessary to provide a method ofplanarizing a dielectric layer using a chemical-mechanical operationcapable of attaining a higher level of planarity through the formationof a shallow dummy pattern.

SUMMARY OF THE INVENTION

[0025] Accordingly, the present invention provides a chemical-mechanicalpolishing method that utilizes a shallow dummy pattern for planarizing adielectric layer. The method is capable of producing a surface with ahigh level of planarity and a shorter polishing time.

[0026] In another aspect, the invention provides a method of reducingthe erosion of dielectric layer through the formation of a shallow dummypattern.

[0027] In one further aspect, the invention provides a method of forminginterconnects such that the shallow dummy pattern is removed as soon asthe interconnects are formed to prevent intra-metal parasiticcapacitance.

[0028] To achieve these and other advantages and in accordance with thepurpose of the invention, as embodied and broadly described herein, theinvention provides a chemical-mechanical polishing method that utilizesa shallow dummy pattern for planarizing a dielectric layer. The methodincludes the steps of first forming a shallow dummy pattern on thedielectric layer, and then coating a patterned photoresist layer overthe dielectric layer. The photoresist layer covers the shallow dummypattern. Thereafter, the photoresist layer is used as a mask to formopenings in other areas of the dielectric layer. These openings expose aportion of the metallic layer underneath the dielectric layer.Subsequently, the photoresist layer is removed to expose the shallowdummy pattern, and then a glue/barrier layer and a conductive layer aresequentially deposited. Next, a chemical-mechanical polishing operationis carried out to remove excess conductive layer and glue/barrier layerabove the dielectric layer as well as the shallow dummy pattern at thesame time. Since the removal rate of glue/barrier layer in each areaabove the dielectric layer is about the same, a highly planar substratesurface is obtained.

[0029] It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary, andare intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention. In the drawings,

[0031]FIGS. 1A through 1E are cross-sectional views showing theprogression of manufacturing steps taken in production of aninterconnect that uses a chemical-mechanical polishing method to removeexcess metal according to a conventional dual damascene process;

[0032]FIGS. 2A through 2C are cross-sectional views showing the stepstaken in production of an interconnect using a chemical-mechanicalpolishing operation that has a higher polishing removal rate for theglue/barrier layer in the open area of a damascene pattern;

[0033]FIGS. 3A through 3G are cross-sectional views showing theprogression of manufacturing steps taken in production of aninterconnect by using a shallow dummy pattern in a chemical-mechanicalpolishing operation according to one preferred embodiment of thisinvention; and

[0034]FIG. 4 is a graph showing the polishing rate of a dielectric layerand the corresponding time needed to remove a glue/barrier layer versuswidth of a conductive line for a pattern having a fixed density.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0035] Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

[0036]FIGS. 3A through 3G are cross-sectional views showing theprogression of manufacturing steps taken in production of aninterconnect by using a shallow dummy pattern in a chemical-mechanicalpolishing operation according to one preferred embodiment of thisinvention.

[0037] First, as shown in FIG. 3A, a conductive layer 112 is formed overa substrate 100. Thereafter, a dielectric layer 114 and an etching stoplayer 116 are sequentially formed over the conductive layer 112. Thedielectric layer 114 can be a silicon oxide (SiO_(x)) layer, and theetching stop layer 116 can be a silicon nitride (SiN_(x)) layer, forexample. Then, a patterned photoresist layer 108 is formed over theetching stop layer 116. The patterned photoresist layer 108 is used formarking out the area where a via opening is formed. Subsequently, theetching stop layer 116 is etched to form an opening using thephotoresist layer 108 as a mask. The etching stop layer 116 is laterused as a mask in patterning out the via opening.

[0038] Next, as shown in FIG. 3B, the photoresist layer 108 is removed,and then another dielectric layer 124 is formed over the etching stoplayer 116.

[0039] Next, as shown in FIG. 3C, another patterned photoresist layer118 is formed over the dielectric layer 124. The patterned photoresistlayer 118 is used for forming a dummy pattern on the open area 129 ofthe damascene pattern. Thereafter, using the photoresist layer 118 as amask, a shallow dummy pattern 120 is formed above the dielectric layer124 using a dry etching method. The shallow dummy pattern 120 is onemajor aspect in this invention. The dummy pattern 120 occupies only asmall fraction of the thickness of the dielectric layer 124 a.Preferably, the shallow dummy pattern 120 has a depth of 300-500 Å.

[0040] In designing the shallow dummy pattern, consideration must bemade regarding the relationship between conductive line width versus thepolishing rate of the dielectric layer and the removal time of theglue/barrier layer. In other words, line width of the dummy pattern inthe open area 129 must be similar to the line width of the conductivelines in the dense area 127 of a damascene pattern.

[0041]FIG. 4 is a graph showing the polishing rate of a dielectric layerand the corresponding time needed to remove a glue/barrier layer versuswidth of a conductive line for a pattern having a fixed density. Infact, FIG. 4 illustrates the relationship when the damascene pattern hasa density fixed at 50%. In FIG. 4, the vertical axis representsrespectively the polishing rate of a dielectric layer and thecorresponding removal time for the glue/barrier layer. The horizontalaxis represents line width. When the line width is small, for example,0.5 μm, distance between neighboring conductive lines is also narrower,since the density of the damascene pattern is fixed. Hence, the removaltime for glue/barrier layer is a smaller value such as T₂, while thepolishing rate of the dielectric layer is a faster value such as V₁. Asline width of conductive lines increases, removal time of theglue/barrier layer is longer. For example, when the line width is about5.2 μm, removal time of the glue/barrier layer is about T₁, but thecorresponding polishing rate of the dielectric layer is lower, such asV₂.

[0042] For example, if the line width in the dense area 127 of adamascene pattern is about 0.5 μm and the line width in the open area129 of a damascene pattern is about 5.2 μm, line width of the dummypattern in the open area 129 should be about 0.5 μm in order to reducethe removal time of the glue/barrier layer in the open area 129. Inother words, the polishing time can be shortened from T₁ to T₂.

[0043] Next, as shown in FIG. 3D, the photoresist layer 118 is removedto expose the dielectric layer 124 a, wherein the dielectric layer 124 ahas a shallow dummy pattern 120 on top.

[0044] Next, as shown in FIG. 3E, a third patterned photoresist layer128 is formed over the dielectric layer 124 a. The patterned photoresistlayer 128 is used for patterning out trench areas. Thereafter, using thephotoresist layer 128 as a mask, a dry etching method is used to patternthe dielectric layer 124 a. Consequently, a portion of the etching stoplayer 116 is exposed and a dielectric layer 124 b having a trench 125within is formed. Subsequently, using the exposed etching stop layer 116as a mask, dry etching of the dielectric layer 114 is carried out. Thus,a portion of the metallic layer 112 is exposed and a dielectric layer114 having a via opening 123 within is formed. All through the dryetching operation, the shallow dummy pattern 120 is covered by thephotoresist layer 128.

[0045] Next, as shown in FIG. 3F, the photoresist layer 128 is removed,and then a glue/barrier layer 121 conformal to the substrate profile isformed above the substrate structure 100. The glue/barrier layer 121,for example, can be a tantalum nitride tantalum nitride, tantalum,titanium and titanium nitride layer or other material with the samefeature as known by someone skilled in the art. Thereafter, a metalliclayer 122 is formed over the glue/barrier layer 121 that also completelyfills the via opening 123 (FIG. 3E), the trench 125 (FIG. 3E) and theshallow dummy pattern 120 (FIG. 3D). The metallic layer 122, forexample, can be a layer of copper.

[0046] Next, as shown in FIG. 3G, a chemical-mechanical polishingoperation is carried out to remove excess metallic layer 122 andglue/barrier layer 121 above the dielectric layer 124 b. Hence, thefilled via opening 123 (FIG. 3E) becomes a plug 122 c, the filledtrenches 125 (FIG. 3E) become conductive lines 122 a, and theglue/barrier layer 121 becomes glue/barrier layers 121 a. Note that theshallow dummy pattern 120 originally on top of the dielectric layer 124b have been completely removed so that the dielectric layer 124 b nowbecomes a dielectric layer 124 c. Due to the removal of shallow dummypattern 120 from the substrate structure, no dummy conductive linesremain. Thus, the invention is capable of preventing the formation ofintra-metal parasitic capacitance.

[0047] The polishing rate of metallic layer 122 is faster than thepolishing rate of the glue/barrier layer 121 in the polishing operationafter excess metallic layer 122 above the dielectric layer 124 b isremoved. This means that the metallic layer and a portion of themetallic layer within the trench 125 near the shallow dummy pattern 120is easier to remove, and thus the glue/barrier layer 121 nearby iseasier to remove, too. Consequently, polishing time can be effectivelyreduced. The polishing operation will stop only when all trace of theshallow dummy pattern is removed. Hence, a highly planar surface isultimately obtained. Furthermore, besides shortening the polishing time,the method is also capable of preventing the erosion of dielectric layerin certain regions.

[0048] The shallow dummy pattern 120 of this invention works in a waysimilar to the dummy pattern 35, which is shown in FIG. 2A. Therefore,the dummy pattern 120 is capable of equating the polishing rate betweenthe dense area 127 and the open area 129 of a damascene pattern in achemical-mechanical polishing operation. However, a conventional dummypattern 35 results in the formation of dummy conductive lines 32 b asshown in FIG. 2C, whereas the shallow dummy pattern 120 of thisinvention disappears in the polishing process. Hence, there is nointra-metal parasitic capacitance problem.

[0049] In summary, major characteristics of this invention include:

[0050] 1. The invention makes the polishing rate between the dense areaand the open area of a damascene pattern roughly the same byestablishing a shallow dummy pattern with a suitable line width in theopen area.

[0051] 2. By forming a shallow dummy pattern on top of a dielectriclayer first and then using a chemical-mechanical polishing operation topolish the dielectric layer, polishing time can be shortened and asurface having a high degree of planarity can be obtained.

[0052] 3. By forming a shallow dummy pattern over the dielectric layer,the dielectric layer erosion while the glue/barrier layer is polishedcan be prevented.

[0053] 4. The shallow dummy pattern is completely removed as soon as themanufacturing of interconnects is complete. Hence, no dummy conductivelines are present, and no intra-metal parasitic capacitance is produced.

[0054] It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

What is claimed is:
 1. A method of planarization, comprising the stepsof: forming a patterned metallic layer over a semiconductor substrate;forming a dielectric layer over the patterned metallic layer; patterningthe dielectric layer to form a plurality of shallow dummy patterns;forming a mask layer over the dielectric layer such that the mask layerexposes a plurality of areas for forming openings while covering theshallow dummy patterns; patterning the dielectric layer again using themask layer as a mask to form openings in the dielectric layer, whereinthe openings expose a portion of the metallic layer; removing the masklayer to expose the shallow dummy patterns; forming a glue/barrier layerover the dielectric layer; forming a conductive layer over theglue/barrier layer, wherein the conductive material completely fills theopenings and the shallow dummy patterns; and performing achemical-mechanical polishing operation to remove excess conductivelayer and glue/barrier layer above the dielectric layer, and at the sametime removing the shallow dummy patterned to obtain a planarizedsurface.
 2. The method of claim 1, wherein the shallow dummy pattern hasa depth of 300 Å-500 Å.
 3. The method of claim 1, wherein the line widthand the line density of the shallow dummy pattern are very similar tothe line width in the areas having openings.
 4. The method of claim 1,wherein the shallow dummy pattern is formed in a low pattern densityareas for forming the openings.
 5. The method of claim 1, wherein thestep of forming the glue/barrier layer includes depositing a materialselected from the group consisting of tantalum nitride, tantalum,titanium and titanium nitride.
 6. The method of claim 1, wherein thestep of forming the conductive layer includes depositing copper.
 7. Themethod of claim 1, wherein the step of forming a mask layer includesdepositing a photoresist material to form a photoresist layer.
 8. Themethod of claim 1, wherein the polishing rate of the glue/barrier layerabove the dielectric layer is the same in all places.
 9. A method ofplanarization, comprising the steps of: forming a patterned metalliclayer over a semiconductor substrate; forming a first dielectric layerover the patterned metallic layer; forming an etching stop layer overthe first dielectric layer that exposes areas for forming via openings;forming a second dielectric layer that has a plurality of shallow dummypatterns over the etching stop layer; forming a photoresist layer overthe second dielectric layer such that the photoresist layer exposesareas for forming a plurality of trench patterns while covering theshallow dummy patterns; patterning the second dielectric layer using thephotoresist layer as a mask until a portion of the etching stop layer isexposed, and then patterning the first dielectric layer using theetching stop layer as a mask until a portion of the metallic layer isexposed, ultimately forming trench patterns within the second dielectriclayer and forming via openings within the first dielectric layer;removing the photoresist layer; forming a glue/barrier layer over theexposed surface of the first dielectric layer and the second dielectriclayer; forming a conductive layer over the glue/barrier layer such thatthe conductive material completely fills the via openings, the trenchesand the shallow dummy patterns; and performing a chemical-mechanicalpolishing operation to remove excess conductive layer and glue/barrierlayer above the second dielectric layer, and at the same time removingthe shallow dummy pattern to obtain a planarized surface.
 10. The methodof claim 9, wherein the shallow dummy pattern has a depth of 300 Å-500Å.
 11. The method of claim 9, wherein the shallow dummy pattern has linewidth very similar to the line width in the trench areas.
 12. The methodof claim 9, wherein the shallow dummy pattern is formed in the lowopening density areas.
 13. The method of claim 9, wherein the step offorming the glue/barrier layer includes depositing tantalum nitride. 14.The method of claim 9, wherein the step of forming the conductive layerincludes depositing copper.
 15. The method of claim 9, wherein thepolishing rate of glue/barrier layer above the second dielectric layeris the same in all places.